Exemplary embodiments of the present invention relate to a semiconductor memory device.
A dynamic random access memory (DRAM) includes a plurality of memory cell units each of which may be configured with one transistor and one capacitor, and data is stored in the capacitor. However, data stored in a capacitor formed on a semiconductor substrate may be lost due to a natural leakage through the semiconductor substrate. Thus, the DRAM performs a refresh operation which refreshes data stored in a memory cell. If the operation of refreshing data stored in the memory cell is not performed stably, data may be damaged or the characteristic of the DRAM with respect to the read operation may be degraded. In addition, the DRAM may malfunction. As the integration degree of the DRAM increases, the number of memory cells to be refreshed in a refresh operation increases and the entire memory cells may not be refreshed through one word line. Hence, a bank is divided into a plurality of cell regions, and a refresh operation is performed on the plurality of cell regions.
As high integration technology of a semiconductor memory device is developed, the number of memory cells and signal lines provided in a single semiconductor memory device is rapidly increasing. In order to integrate the increasing memory cells and signal lines within a limited space, the critical dimension of an internal circuit of the semiconductor memory device has been reduced and the size of a memory cell has been gradually reduced. For these reasons, memory cells of a semiconductor memory device are more likely to be defective. Therefore, a redundancy device for repairing defective memory cells is provided within a semiconductor memory device so that the semiconductor memory device can be manufactured with a high yield in spite of such defective memory cells. The redundancy device includes redundancy memory cells and fuses for programming repair addresses corresponding to defective memory cells.
A variety of tests are performed after a fabrication process of a semiconductor memory device is completed. In a case in which a memory cell determined as a defective memory cell can be repaired, the defect of the memory cell is repaired by replacing the defective memory cell with a redundancy memory cell. That is, a programming is performed within an internal circuit to replace the address of the defective memory cell with the address of the redundancy memory cell. Accordingly, when the address, i.e., the repair address, corresponding to the defective memory cell is inputted, the defective memory cell is replaced with the redundancy memory cell. Thus, the semiconductor memory apparatus performs a normal operation.
Hereinafter, a method of refreshing a bank which is divided into two cell regions will be described as an example, and concerns which may arise when a word line is replaced through a refresh operation will be described.
FIG. 1 is a block diagram illustrating a refresh operation and concerns regarding the refresh operation.
Referring to FIG. 1, a semiconductor memory device includes a bank 100 which is divided into a first cell region 110 and a second cell region 120. In the bank 100, the first cell region 110 and the second cell region 120 correspond to an upper bank and a lower bank, respectively. In FIG. 1, a first signal A is a row active signal which activates a word line of the upper bank 110, and a second signal B is a row active signal which activates a word line of the lower bank 120.
As illustrated in a first operation diagram 101, when a refresh command is inputted, word lines 111 and 121 corresponding to row addresses counted by an address counting unit (not shown) are simultaneously activated within the upper bank 110 and the lower bank 120. That is, when the refresh command is inputted once, one word line 111 of the upper bank 110 and one word line 121 of the lower bank 120 are simultaneously activated, and a plurality of memory cells coupled to the activated word lines 111 and 121 are refreshed. The first line 111 is a word line activated by the first signal A, and the second line 121 is a word line activated by the second signal B.
The upper bank 110 and the lower bank 120 include a plurality of redundancy word lines for replacing word lines having defects. However, in a case in which the bank is divided into the upper bank 110 and the lower bank 120 and the refresh operation is simultaneously performed on the upper bank 110 and the lower bank 120, the upper bank 110 cannot use the redundancy word lines of the lower bank 120, and the lower bank 120 cannot use the redundancy word lines of the upper bank 110. The reasons are described below.
It is assumed in a second operation diagram 102 that a defect occurs in one word line 111A of the upper bank 110 and thus the word line 111A is replaced with a redundancy word line 121A. An arrow 103 represents that the defect occurs in the word line 111A of the upper bank 110 and the word line 111A is replaced with the word line 121A of the lower bank 120.
If a row address corresponding to the defective word 111A of the upper bank 110 is inputted, the redundancy word line 121A of the lower bank 120 is activated by the first signal A while another word line 121B of the lower bank 120 corresponding to the row address is activated by the second signal B. That is, if the defective word line 111A of the upper bank 110 is replaced with the redundancy word line 121A of the lower bank 120, two word lines 121A and 121B may be simultaneously activated in the lower bank 120 during the refresh operation. Therefore, data stored in memory cells coupled to the activated word lines 121A and 121B are simultaneously loaded on the same bit line. In other words, two data are loaded on one bit line. Consequently, an error may occur when the two data are different from each other.